1. Field of the Invention
The present invention generally relates to a method for forming a polysilicon plug of a semiconductor device, and a method for forming a polysilicon plug of a semiconductor wherein an interlayer insulating film is polished until a hard mask film is exposed and then a barrier film is deposited on the entire surface of the hard mask film and used as a polishing barrier film when a landing plug contact hole is formed, thereby improving the margin of the hard mask film of the peripheral circuit region so that a wordline is not exposed.
2. Description of the Prior Art
FIGS. 1a to 1i are cross-sectional diagrams illustrating a conventional method for forming a polysilicon plug of a semiconductor device.
Referring to FIG. 1a, a stacked pattern of a wordline 12 and a hard mask film 14 is formed on a semiconductor substrate 10 comprising a cell region C and a peripheral circuit region P. Here, the hard mask film 14 is formed of a nitride film, and its thickness is t1.
Next, a nitride film or an oxide film (not shown) is formed on the entire surface of the resulting structure, and a spacer 16 are formed on a sidewall of the stacked pattern of the wordline 12 and the hard mask film 14 by blanket-etching the nitride film or the oxide film.
Referring to FIG. 1b, an interlayer insulating film 18 is formed by filling an oxide film such as a BPSG (boron phosphorous silicate glass) oxide film on the entire surface of the resulting structure.
Referring to FIG. 1c, a CMP process is performed only on the interlayer insulating film 18 of the cell region C while the cell region C is open by using a cell open mask in order to facilitate a subsequent planarization process by alleviating a region difference between the interlayer insulating film 18 of the cell region C and the interlayer insulating film 18 of the peripheral circuit region P.
Referring to FIG. 1d, the interlayer insulating film 18 is planarized by performing a CMP process on the entire surface of the interlayer insulating film 18 having the alleviated region difference. Here, the thickness of the planarized interlayer insulating film 18 is t2 from the hard mask film 14.
Referring to FIG. 1e, a photoresist film (not shown) is deposited on the interlayer insulating film 18, and a photoresist film pattern 20 is formed by selectively exposing and developing the photoresist film.
Referring to FIG. 1f, a landing plug contact hole is formed by selectively etching the lower interlayer insulating film 18 using the photoresist film pattern 20 as an etching mask so that the stacked pattern of the wordline 12 and the hard mask film 14 remains in the contact hole region.
As a result, the upper portion of the hard mask film 14 is partially removed because the stacked pattern is exposed when the contact is formed, and the thickness of the hard mask film 14 is reduced from t1 to t3. The interlayer insulating film 18 which remains on the cell region C is partially removed by the CMP process, and the thickness of the interlayer insulating film 18 is reduced from t2 to t4.
Thereafter, the remaining portion of the photoresist film pattern 20 after the etching process is removed using O2 plasma.
Then, a capping layer (not shown) is formed by depositing a USG (Undoped Silicate Glass) film on the entire surface of the resulting structure, and the capping layer remains only on the surface of the stacked pattern by etching back the USG film so that the hard mask film 14 may not be damaged in a subsequent process.
Referring to FIG. 1g, the landing plug contact hole is filled by depositing a polysilicon film 24 on the entire surface of the resulting surface, which results in a step difference of t5 due to the previous process difference. That is, the polysilicon film 24 has the step difference of t5 in the contact, and has a thickness of t6 from the hard mask film 14.
Referring to FIG. 1h, the polysilicon film 24 is blanket-etched so that the polysilicon film 24 of the cell region C is partially removed and the polysilicon film 24 of the peripheral circuit region P is completely removed.
Referring to FIG. 1i, a CMP process is performed on the polysilicon film 24, the interlayer insulating film 18, the hard mask film 14 under the interlayer insulating film 18 of the cell region C and the interlayer insulating film 18 of the peripheral circuit region P by using the hard mask film 14 on the cell region C as a polishing barrier film until the hard mask film 14 on the cell region C is exposed. Here, the removing process is performed on the polysilicon film 24 by a thickness of t6 to separate the polysilicon film 24 into regions P1 and P2.
As a result, a polysilicon plug 26 having the completely separated regions P1 and P2 is formed. Here, the wordline is exposed by loss of the hard mask film 14 of the peripheral circuit region P. In this way, the exposed wordline causes misalignment in a subsequent process. In addition, a bridge is formed between the wordline and storage node contact or leakage current increases, which results in fail of devices.
To minimize loss of a hard mask film and secure a bottom area of an open contact are generally required when a landing plug contact hole is formed by etching an interlayer insulating film via a SAC process. Here, the loss of the hard mask film is minimized because the margin of the hard mask film resulting from a CMP process performed to form a plug by separating a deposited polysilicon film may cause fail of devices.
In order to overcome the margin problem of the hard mask film, a capping layer is formed by depositing a USG (undoped silicate glass) film having a poor step coverage before etching the hard mask film, and then an etch-back process is performed on the capping layer.
When a landing plug contact hole is formed via a SAC process using ArF as a light source, the hard mask film is lost at a thickness ranging about from 800 to 900 Å. The loss of the hard mask film reaches over about 200 Å than in a process using a KrF as a light source.
As a result, the thickness of the hard mask film becomes thicker to compensate the loss of the hard mask film, which affects the subsequent process of forming the interlayer insulating film and security of bottom CD of the contact. As described above, since the USG film is deposited to protect the hard mask film and it makes control of the thickness of the interlayer insulating film in the contact more difficult, partial contacts are not open in the conventional KrF process. Accordingly, it is important to embody a structure where a capping layer is not formed for configuration of a landing plug contact hole structure.